PL EN


Preferencje help
Widoczny [Schowaj] Abstrakt
Liczba wyników
2014 | 2 | 871--878
Tytuł artykułu

A New Mode of Operation for Arbiter PUF to Improve Uniqueness on FPGA

Warianty tytułu
Języki publikacji
EN
Abstrakty
EN
Arbiter-based Physically Unclonable Function~(PUF) is one kind of the delay-based PUFs that use the time difference of two delay-line signals. One of the previous work suggests that Arbiter PUFs implemented on Xilinx Virtex-5 FPGAs generate responses with almost no difference, i.e. with low uniqueness. In order to overcome this problem, Double Arbiter PUF was proposed, which is based on a novel technique for generating responses with high uniqueness from duplicated Arbiter PUFs on FPGAs. It needs the same costs as 2-XOR Arbiter PUF that XORs outputs of two Arbiter PUFs. Double Arbiter PUF is different from 2-XOR Arbiter PUF in terms of mode of operation for Arbiter PUF: the wire assignment between an arbiter and output signals from the final selectors located just before the arbiter. In this paper, we evaluate these PUFs as for uniqueness, randomness, and steadiness. We consider finding a new mode of operation for Arbiter PUF that can be realized on FPGA. In order to improve the uniqueness of responses, we propose 3-1 Double Arbiter PUF that has another duplicated Arbiter PUF, i.e. having 3 Arbiter PUFs and output 1-bit response. We compare 3-1 Double Arbiter PUF to 3-XOR Arbiter PUF according to the uniqueness, randomness, and steadiness, and show the difference between these PUFs by considering the mode of operation for Arbiter PUF. From our experimental results, the uniqueness of responses from 3-1 Double Arbiter PUF is approximately 50%, which is better than that from 3-XOR Arbiter PUF. We show that we can improve the uniqueness by using a new mode of operation for Arbiter PUF.(original abstract)
Rocznik
Tom
2
Strony
871--878
Opis fizyczny
Twórcy
  • The University of Electro-Communications, Japan
autor
  • Fujitsu Laboratories Ltd.
  • The University of Electro-Communications, Japan
  • The University of Electro-Communications, Japan
Bibliografia
  • Anderson J. H., "A PUF design for secure FPGA-based embedded systems," in Proceedings of ASP-DAC, 2010, pp. 1-6, http://dx.doi.org/10.1109/ASPDAC.2010.5419927.
  • Gassend B., Lim D., Clarke D. E., van Dijk M., and Devadas S., "Identification and authentication of integrated circuits." Concurrency and Computation: Practice and Experience, pp. 1077-1098, 2004, http://dx.doi.org/10.1002/cpe.805.
  • Handschuh H., Schrijen G. J., and Tuyls P., "Hardware intrinsic security from physically unclonable functions." in Towards Hardware-Intrinsic Security, 2010, pp. 39-53, http://dx.doi.org/10.1007/978-3-642-14452-3 2.
  • Hori Y., Katashita T., and Kobara K., "Performance Evaluation of Physical Unclonable Functions on Kintex-7 FPGA (in Japanese)," in IEICE Technical report of RECONF, 2013.
  • Hori Y., Yoshida T., Katashita T., and Satoh A., "Quantitative and Statistical Performance Evaluation of Arbiter Physical Unclonable Functions on FPGAs," in Proceedings of ReConFig, 2010, pp. 298-303, http://dx.doi.org/10.1109/ReConFig.2010.24.
  • Lim D., Lee J. W., Gassend B., Suh G. E., van Dijk M., and Devadas S., "Extracting secret keys from integrated circuits," IEEE Trans. Very Large Scale Integr. Syst., pp. 1200-1205, 2005, http://dx.doi.org/10.1109/TVLSI.2005.859470.
  • Machida T., Nakasone T., and Sakiyama K., "Evaluation Method for Arbiter PUF on FPGA and Its Vulnerability (in Japanese)," in IEICE Technical report of ISEC, 2013.
  • Machida T., Yamamoto D., Iwamoto M., and Sakiyama K., "A Study on Uniqueness of Arbiter PUF Implemented on FPGA (in Japanese)," in Symposium record of SCIS, 2014.
  • Maes R., "Physically Unclonable Functions - Constructions, Properties and Applications," in Springer, 2013, http://dx.doi.org/10.1007/978-3-642-41395-7.
  • Maiti A., Gunreddy V., and Schaumont P., "A Systematic Method to Evaluate and Compare the Performance of Physical Unclonable Functions," in Embedded Systems Design with FPGAs, 2013, pp. 245-267, http://dx.doi.org/10.1007/978-1-4614-1362-2 11.
  • National Institute of Advanced Industrial Science and Technology, "Side-channel Attack Standard Evaluation Board (SASEBO)," http://www.risec.aist.go.jp/project/sasebo/.
  • Paral Z. S. and Devadas S., "Reliable and efficient PUF-based key generation using pattern matching." in in Proceedings of HOST. IEEE Computer Society, 2011, pp. 128-133, http://dx.doi.org/10.1109/HST.2011.5955010.
  • Ravikanth P. S., "Physical one-way functions," Ph.D. dissertation, 2001, http://dx.doi.org/10.1126/science.1074376.
  • Ruhrmair U., Sehnke F., Solter J., Dror G., Devadas S., and Schmidhuber J., "Modeling Attacks on Physical Unclonable Functions," in Proceedings of CCS, 2010, pp. 237-249, http://dx.doi.org/10.1145/1866307.1866335.
  • Saifullah S., Khawaja A., Hamza, Arsalan, Maryam, and Anum, "Keyless car entry through face recognition using FPGA," in Proceedings of FITME, 2010, pp. 224-227, http://dx.doi.org/10.1109/FITME.2010.5654862.
  • Seki K., Hori Y., and Imai H., "Implementation and Evaluation of Physical Unclonable Function on SASEBO-GII (in Japanese)," in Symposium record of SCIS, 2010.
  • Suh G. E. and Devadas S., "Physical Unclonable Functions for Device Authentication and Secret Key Generation," in Proceedings of DAC, 2007, pp. 9-14, http://dx.doi.org/10.1145/1278480.1278484.
  • Tuyls P., Skoric B., and Kevenaar T., Security with Noisy Data: Private Biometrics, Secure Key Storage and Anti-Counterfeiting. Springer-Verlag New York, Inc., 2007, http://dx.doi.org/10.1007/978-1-84628-984-2.
  • XILINX, "Virtex-5 FPGA User Guide," http//www.xilinx.com/support/documentation/user guides/ug190.pdf.
Typ dokumentu
Bibliografia
Identyfikatory
Identyfikator YADDA
bwmeta1.element.ekon-element-000171335475

Zgłoszenie zostało wysłane

Zgłoszenie zostało wysłane

Musisz być zalogowany aby pisać komentarze.
JavaScript jest wyłączony w Twojej przeglądarce internetowej. Włącz go, a następnie odśwież stronę, aby móc w pełni z niej korzystać.